In various memories, data may be read from memory sections and provided to external devices via lines, such as global data lines. Typically, sense amplifiers are located at an end of these lines and are configured to sense data on the lines in response to a signal, such as a strobe signal.
As memory density and complexity has increased over time, the data lines extending through memories have increased in both length and number. Line length in particular has been a design constraint. For example, as the further a section coupled to a line is located from the sense amplifier, also coupled to that line, the greater the amount of time that is required for the section to drive the line to a condition that may be accurately sensed by the sense amplifier.
In conventional systems, the time at which a sense amplifier senses data on a line is delayed by a predetermined amount relative to receipt of a command to ensure accurate sensing of data. Typically, a worst case delay is implemented in each operation such that even the furthest section on a line may drive lines to conditions sufficient for accurate sensing before a sense amplifier is enabled.
By implementing this delay, however, power may be needlessly consumed. Specifically, the closer a section is located relative to a sense amplifier, the less time that is required for the lines to be driven to the condition sufficient for accurate sensing by the sense amplifier, and, as a result, the more time that a section continues to drive the lines beyond the condition until the sense amplifier is enabled unnecessarily consumes power.